LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity Multiplexor16a4 is
  port(
  vector3, vector2, vector1, vector0: in std_logic_vector( 3 downto 0);
  control1, control0 : in std_logic;
  salida : out std_logic_vector (3 downto 0)
  );     
end;

architecture aMultiplexor16a4 of Multiplexor16a4 is
begin
  process (vector0, vector1, vector2, vector3,control0, control1 )
  begin
    if control0 ='0' and control1 ='0'then
      salida <=  vector0;
  elsif control0 ='1' and control1 ='0'then
      salida <=  vector1;
  elsif control0 ='0' and control1 ='1'then
      salida <=  vector2;
  elsif control0 ='1' and control1 ='1'then
      salida <=  vector3;
    end if ;
  end process ;
end;
